Free Digital Verification Technologies Seminar
Mastering FPGA Verification: From Bottleneck to Confidence
Tuesday, 21st of July at Hoogeind Manor, Somerset West
Thursday, 23rd of July at Attache Lodge, Midrand
The increasing complexity of modern FPGA designs, driven by high-speed interfaces, heterogeneous architectures, and multi-clock domain systems, is placing unprecedented pressure on verification processes.
While design implementation flows continue to improve, verification has emerged as the primary bottleneck in achieving reliable and high-quality FPGA systems.
This seminar is carefully designed to provide participants with a comprehensive understanding of advanced FPGA verification methodologies across the full development lifecycle—from RTL to bitstream.
By leveraging Siemens’ Questa™ simulation, formal, and static verification solutions, attendees will gain practical knowledge and hands-on experience to effectively verify, validate, and debug complex FPGA designs
Our Guest Speaker is Faïçal Chtourou, a Digital Verification Technology specialist at Siemens EDA in Germany. Prior to joining Siemens, Faïçal was an ASIC verification engineer with Infineon Technologies and then the Hardware Verification Manager at HyperStone.
Seminar Agenda
From RTL to Bitstream: Why FPGA Verification is Now the Bottleneck (and How to Fix It)
08:30 → 10:00
This session introduces the key challenges of modern FPGA verification, highlighting how increasing design complexity, multi-clock domains, and advanced protocols have made verification the primary bottleneck in project success. A representative case study will be used to illustrate the complete verification flow and expose real-world challenges across the design lifecycle.
Participants will learn:
- Why verification has become the bottleneck in FPGA development
- Directed testing vs. constrained-random verification approaches
- Combining simulation and formal for hybrid verification
- Best practices for building robust and scalable verification flows
Beyond Simulation: Achieving Confidence in FPGA Designs with Formal Techniques
10:30 → 12:00
This session focuses on advanced verification methodologies, emphasizing RTL quality as the foundation of any successful FPGA project. It explores how linting, advanced static analysis, and formal verification techniques can be combined to improve design robustness and confidence.
Participants will discover:
- The role of linting and advanced linting in early bug detection and RTL quality improvement
- How formal verification detects corner-case bugs beyond simulation
- How to effectively combine simulation and formal techniques
- Strategies to improve coverage and accelerate verification closure
Practical Sessions
13:00 → 16:00
Hands-on sessions designed to reinforce the concepts introduced in the morning through practical exercises and real-world scenarios.
- Visualizer Lab
- Advanced debugging with Visualizer
- Waveform analysis and root-cause identification
- Performance profiling and bottleneck analysis
- Coverage analysis and verification closure
- Questa Static & Formal Verification Labs
- Linting and static analysis for early bug detection
- Advanced linting for identifying complex RTL issues
- Using Questa Formal and Static solution in CI flow
This lab focuses on improving RTL quality and leveraging static and formal verification techniques to detect issues early and enhance overall design robustness.