Overview
The Actel Libero training is a 2 day course. Using a design example, each student is guided through the complete flow of a hierarchical design. The course consists of a discussion and hands-on VHDL labs and each student will come away with the ability to use Actel's integrated Libero environment to take a design from conception to a functioning Actel FPGA.

Objectives

• Project creation with Libero's Integrated Design Environment
• HDL and schematic entry with HDL Editor and ViewDraw
• Block generation and synthesis with Actel's ACTgen and Synplicity's Synplify
• Automatic test bench generation with SynaptiCAD's WaveFormer Lite
• Design capture and simulation using Mentor Graphics' ModelSim Simulator
• Design layout (place and route) and timing analysis with Actel's Designer software
• FPGA programming and debugging with Actel's Windows Programming and Silicon Explorer tools

For futher information and booking contact training@asic.co.za or Francois Labuschagne at ASIC Design Services.