HDL Designer is a complete design and management solution that includes all the point tools of the HDL Designer Series. It allows you to standardize on a toolset that can be used across your company, and share designs and designers around the office or around the world. HDL visualization and creation tools, along with automatic documentation features, foster a consistent style of HDL for improved design reuse, so you can fully leverage existing IP, find economies that you didn't know existed, and cut time-to-market and development costs company-wide.
This course teaches you to use HDL Designer Series effectively in your FPGA or ASIC design process. The lectures take you through the HDL Designer Series design flow. This includes modeling the design with both graphics and text, generating HDL, and then simulating and animating the design to verify behavior. Hands-on lab exercises will reinforce lecture topics and provide you with extensive tool usage experience.
- Set up libraries to hold your designs
- Model hierarchy and connectivity using block diagrams and IBD
- Model finite state machines with state diagrams
- Model sequential processes with flow charts
- Model combinatorial circuits with truth tables
- Create and edit component symbols
- Generate HDL for your graphical/textual design
- Compile your design for simulation
- Simulate your design using ModelSim�
- Animate and debug your design
- Reuse components
- Convert existing HDL designs into graphical/textual HDL Designer Series designs
- Create test benches
- Manage your design using version management
- Interface with a wide range of downstream tools (compilers, simulators, and synthesis tools)
For futher information and booking contact firstname.lastname@example.org or Francois Labuschagne at ASIC Design Services.